Design of low power transceiver on Spartan-3 and Spartan-6 FPGA

Yousef A. Baker, El-Ebiary and Keshav, Kumar and Bishwajeet, Pandey (2019) Design of low power transceiver on Spartan-3 and Spartan-6 FPGA. International Journal of Innovative Technology and Exploring Engineering (IJITEE), 8 (12S2). pp. 27-30. ISSN 2278-3075

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In this research work, a low power transceiver is designed using Spartan-3 and Spartan-6 Field-Programmable Gate Array (FPGA). In this work, a Universal Asynchronous Receiver Transmitter (UART) device is used as a transceiver. The implementation of UART is possible with EDA tools called Xilinx 14.1 and the results of the power analysis are targeted on Spartan-3 and Spartan-6 FPGA. The variation of different power of chips that are fabricated on FPGA for e.g., Input/Output (I/O) power consumption, Leakage power dissipation, Signal power utilization, Logic power usage, and the use of Total power, is observed by changing the voltage supply. This research work shows how the change in voltage influence the power consumption of UART on Spartan-3 and Spartan-6 FPGA devices. It is observed that Spartan-6 is found to be more powerefficient as voltage supply increases.

Item Type: Article
Uncontrolled Keywords: Spartan-3, Spartan-6, Power, Voltage, FieldProgrammable Gate Array (FPGA), Universal Asynchronous Receiver Transmitter (UART)
Subjects: Q Science > QA Mathematics > QA75 Electronic computers. Computer science
Divisions: Faculty of Informatics & Computing
Depositing User: Fatin Safura
Date Deposited: 03 Apr 2022 03:59
Last Modified: 10 May 2022 08:21

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